1. Field of the Invention
The present invention relates to an instantaneous switching unit and switching method for a delay/priority control buffer, in which phase adjustment cell is used to switch the operational state of the multiplexed delay/priority control buffer in an ATM switch.
2. Description of the Related Art
In a transmission system of ATM (asynchronous transmission mode), instantaneous switching is necessary for preventing lack and redundancy of signal cell, when switching the operational state of a delay/priority control buffer which is multiplexed for the purpose of improving reliability.
The conventional instantaneous switching unit for use in an ATM switch, resets a main signal cell reserving memory of a standby buffer at the execution of switching, using phase adjustment cell, for the purpose of adjusting the phase between a main signal cell reserving memory of an operational buffer section controlling transmission of signal cell, the operational buffer section being in the operating state, and a main signal cell reserving memory of the standby buffer section not controlling transmission of signal cell, the standby buffer section not being in the operating state.
As this kind of the conventional technique, for example, "A redundant switching method of an ATM switch" is disclosed in Japanese Patent Publication Laid-Open (Kokai) No. Heisei 4-86043. The conventional instantaneous switching unit will be, hereinafter, described with the accompanying drawings.
FIG. 4 is a block diagram showing a constitution of an ATM switch with the conventional instantaneous switching unit for a delay/priority control buffer mounted thereon.
As illustrated in FIG. 4, the ATM switch is provided with an operational buffer section 10 and a standby buffer section 20, each section including a plurality of priority buffers 11 to 1n and 21 to 2n respectively. The respective priority buffers 11 to 1n as well as the priority buffers 21 to 2n have the same structure.
The conventional instantaneous switching unit comprises a phase adjustment cell detecting circuit 31 for detecting phase adjustment cell out of input cell, a main signal cell reserving memory 111 for storing received cell, a writing address counter 112 and a reading address counter 113 for controlling the main signal cell reserving memory 111, a writing address reserving circuit 114 for reserving a writing address, a staying cell amount arithmetic circuit 115 for measuring the amount of main signal cell, which is not subject to the phase adjustment, staying within the main signal cell reserving memory 111, and a reading stop signal creating circuit 40 for transmitting a reading stop signal for controlling readout of the cell in the standby buffer section 20, which are mounted on the operational buffer section 10, and further comprises a phase adjustment cell detecting circuit 32, a main signal cell reserving memory 211, a writing address counter 212 and a reading address counter 213, which are mounted on the standby buffer section 20. Of the above components, the main signal cell reserving memory 111, the writing address counter 112, the reading address counter 113, the writing address reserving circuit 114 and the staying cell amount arithmetic circuit 115 are provided in each priority buffer 11 to 1n. The main signal cell reserving memory 211, the writing address counter 212 and the reading address counter 213 are provided in each priority buffer 21 to 2n.
An operation of instantaneous switching for a delay/priority control buffer in the conventional ATM switch will be described this time.
When the phase adjustment cell for instructing switching of a delay/priority control buffer is respectively entered into the operational buffer 10 and the standby buffer 20, the phase adjustment cell detecting circuits 31 and 32 detect the entered phase adjustment cell, so to perform a switching operation.
In the operational buffer section 10, the phase adjustment cell detecting circuit 31, upon detecting the phase adjustment cell, notifies the writing address reserving circuit 114 of a write trigger signal. The phase adjustment cell is sent from the phase adjustment cell detecting circuit 31 to the priority buffers from the highest priority buffer 11 in sequence, to be written in the main signal cell reserving circuit 111 thereof. The writing address reserving circuit 114 reserves the counter value of the writing address counter 112 at the time of receiving the write trigger signal from the phase adjustment cell detecting circuit 31.
During the switching operation, when the main signal cell having arrived before the issue of the write trigger signal stays in the lower priority buffer of the priority buffers 11 to 1n, readout is performed from the lower priority buffer where the main signal cell has been received before the issue of the write trigger signal, even if the main signal cell having arrived after the issue of the write trigger signal stays in the higher priority buffer of the priority buffers 11 to 1n.
Upon receipt of the write trigger signal, the staying cell amount arithmetic circuit 115 makes a comparison between the counter value of the writing address counter 112 reserved in the writing address reserving circuit 114 and the counter value of the reading address counter 113, and supplies the staying amount information signal about the cell which has been written in the main signal cell reserving memory 111 earlier than the phase adjustment cell until the reading address conforms to the reserved writing address. The reading stop signal creating circuit 40 receives and supervises each staying cell amount information signal supplied from each staying cell amount arithmetic circuit 115 of all the priority buffers 11 to 1n, and supplies the reading stop signal until each comparison value of all the staying cell amount arithmetic circuits 115 becomes "0". The supplied reading stop signal is sent to each reading address counter 213 of the priority buffers 21 to 2n in the standby buffer section 20.
While, in the standby buffer section 20, the phase adjustment cell detecting circuit 32, upon detecting the phase adjustment cell, notifies each writing address counter 212 in all the priority buffers 21 to 2n of the writing counter reset signal. The respective priority buffers 21 to 2n, upon receipt of the writing counter reset signal from the phase adjustment cell detecting circuit 32, reset the respective writing address counters 212 to write the cell arriving later than the phase adjustment cell therein from the address initial value in sequence.
Receiving the reading stop signal supplied from the reading stop signal creating circuit 40 of the operational buffer section 10, the reading address counter 213 of the standby buffer section 20 is reset to return the address to the initial value. The reading address counter 213 stops counting while receiving the reading stop signal. If the entry of the reading stop signal has been finished, it starts readout of the cell reserved in the main signal cell reserving circuit 211, from the address initial value.
However, the conventional instantaneous switching unit for a delay/priority control buffer as mentioned above, resets all the priority buffers of the standby buffer section to supply all the cell staying in the operational buffer section before the phase adjustment cell enters there, by priority. Therefore, if main signal cell, after the input of the phase adjustment cell, enters the higher priority buffer of the operational buffer section than the priority buffer where the cell has already stayed, the accurate priority for the output sequence of the cell cannot be guaranteed in the conventional unit.